The present invention relates to a semiconductor device and a manufacturing method thereof, in particular, to a semiconductor device equipped with CMOSFET having a high-k/metal gate structure and a manufacturing method of the device.
In order to improve an integration density and performance of semiconductor devices, miniaturization of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), which is a constituent component of the semiconductor devices, has been continuously progressing. With realization of miniaturization, however, an influence of a short-channel effect is increasing. Control of this influence is therefore considered to be important. As a measure against this problem, high-k (high dielectric constant) gate insulating film/metal gate structures are known. In these structures, sufficient thickness of the insulating film enables to decrease a leakage current caused by a quantum tunneling effect and at the same time, use of the high-dielectric-constant insulating film enables to raise the amount of current. In addition, use of a metal gate in combination is effective for suppressing phonon oscillation.
In the typical gate first process, gates of CMOSFET having high-k/metal gate structures are formed by the following manufacturing process. First, after deposition of either an n type or a p type gate metal, the gate metal is removed by etching from a region having a polarity opposite thereto. Then, a metal having a polarity opposite to that of the metal deposited first is deposited over the metal removed region. A substance (typically, poly-Si or W) for making gates of equal height or equal resistance is deposited, followed by gate etching to form the gates.
When the typical gate first process as described above is employed, however, a dual metal gate is formed using metals having different work functions for the n type and p type, respectively. This means that materials different in physical and chemical properties should be etched simultaneously, leading to a problem, that is, difficulty in processing.
As a resolution of this problem, there is known a method of forming a capping layer on the high-k film and controlling the work function by using one gate metal. In this CMOSFET using the capping layer, a gate is obtained by forming a high-k gate insulating film, depositing a capping layer, removing the capping layer from a region of a polarity which does not need the capping layer, depositing a gate metal, depositing poly-Si or W, and then etching.
The technologies related to the above description are disclosed in the following Patent Documents 1 and 2, and Non-patent Document 1.    [Patent Document] U.S. Pat. No. 6,545,324    [Patent Document 2] Japanese Unexamined Patent Publication No. 2007-200946    [Non-patent Document 1] IEDM2007, “Single Metal/Dual High-k Gate Stack with Low Vth and Precise Gate Profile Control for Highly Manufacturable Aggressively Scaled CMISFETs”, Mise, N et. al, pp 527-530